P. Anbarasan ¹, K. Hariharan ¹, R. Parameshwaran ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur- 613401, Tamil Nadu, IN

Abstract

In this paper, low power low voltage Op-amp which forms the basic building block for various devices is designed by making the transistors of the Op-amp to operate in sub-threshold region. Now-a-days portable electronic devices are of great demand which thereby increases the demand for low power and low voltage design of devices. Conventionally, two stage op-amps are used which requires higher power with comparatively low gain. In order to overcome this, operation of devices in sub-threshold region is carried out which requires low power comparatively. Initially, the design of conventional Op-amp is designed using CADENCE Virtuoso tool GPDK 180nm with a supply voltage of 1.8V and the corresponding gain, phase margin, power of the conventional Op-amp is observed and then, Op-amp with transistors operating in sub threshold region is designed using CADENCE Virtuoso tool GPDK 180nm with a supply voltage of 1.8V and the corresponding gain, phase margin, power is observed. The comparison between these two observations are made and presented. These low power high gain devices are used in various applications like ADC/DAC devices and many medical applications.

Keywords

Op-amp, Phase Margin, Gain, Sub-Threshold Region.

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A. Naveena Venancias ¹, K. Hariharan ¹, R. Parameshwaran ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Sigma delta ADC is mainly used in resolution based application. But the gain of the sigma delta modulator is low. The main objective of the paper is to design the comparator with high gain. Comparator with low gain cannot drive the load effectively through the entire circuit. This paper was designed and simulated using 180 nm process technology (GPDK 180 nm library) in CADENCE Virtuoso Analog Design Environment. In sigma delta ADC, each block should drive the load effectively to the entire circuit. So that the output will come accurately and delay will be less. Based on that concept, need to design the comparator that can be used in sigma delta ADC. In this point of view, some comparators are analysed. In this paper, analyse the performance of regenerative comparators and op-amp based comparators. And find which will efficient comparator for using at sigma delta modulator. Dynamic comparator, double tail comparator, modified double tail comparator are analysed. The gain of these operational amplifiers are low. So high gain based operational amplifier should be designed. For that, first one op-amp was designed which has 84 dB gain. Using this opamp, one comparator was designed. This comparator has high gain. So it can be used for sigma delta ADC for drive the load. And also it meets certain other constraints like speed and moderate power.

Keywords

CMOS, Opamp Based Comparator, Regenerative Comparators, Sigma Delta ADC, UDSM CMOS Technology.

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